1. Field of the Invention
The present invention is directed to a logic module for generating unequiprobable random patterns for supporting the self-test of integrated circuits, whereby basic cells are provided which contain register cells and gates suitable for a shift mode, and which, with the assistance of control signals and upon utilization of the gates, allows the operation of the register cells as a normal register, as a shift register or as a linear feedback shift register.
2. Description of the Prior Art
Large scale integrated (LSI) digital circuits must be tested after manufacture for operability since the manufacturing process is susceptible to defects and only some of the circuits usually function in accordance with prescribed specifications. Given custom specific circuits in small or moderate additions, this production test can govern the overall costs of the circuit. It is therefore an important object to keep this test as short and as uninvolved as possible.
It is well known in the art to design circuits such that the production test is supported. In particular, numerous methods are applied which promote the self-test procedure with random patterns (for example, IEEE Design and Test, April 1985, pp. 21-28). They are all based on the fact that an arbitrary digital circuit can typically be separated into storage elements, for example register cells, and into combinational circuits. The register cells are provided with an auxiliary equipment with whose assistance the register cells can be interconnected such that they are employable for the self-test procedure. The combination of this auxillary equipment and a register cell shall be referred to as a basic cell herein below. A basic cell or a plurality of basic cells can be interconnected to form the logic module.
As examples, FIG. 1 illustrates two combinational logic systems SN1 and SN2 in which logic modules R1 and R2 composed of basic cells are arranged. Suitable random patterns are generated for the combinational logic system with the assistance of these logic modules R1 and R2 in the test mode and the test responses of the preceding combinational logic system are evaluated. The test execution for the circuit of FIG. 1 is therefore composed of two phases. In the first phase, the logic module R1 generates random patterns for the combinational logic system SN1 and the logic module R2 evaluates the responses of the combination logic system SN1. In the second phase, the logic module R2 generates the patterns for the combinational logic system SN2 of whose response is evaluated by the logic module R1.
This additional test function can be executed with the assistance of the register cells present in the arbitrary digital circuit and with the assistance of the auxillary equipment in that the register cells can be operated as linear feedback shift registers with the assistance of the auxillary equipment and can therefore generate pseudo-random patterns wherein each bit place of the pattern becomes a logical "1" with the probability of 0.5. Registers of this type can also evaluate test responses with parallel signature analysis. Combinations of basic cells (logic module) can be operated such as is known, for example, from the German patent No. 29 02 375, fully incorporated herein by this reference.
The invention disclosed therein is directed to a logic module for a test-friendly, integrated digital circuit with whose assistance hardware-associated test patterns can be generated within the circuit under test and with whose assistance internally-arising test data can be monitored in parallel. Two types of basic cells composed of register cells and gates are provided, these being capable of being operated as normal registers, as shift registers and as feedback shift registers. Uniformly distributed random patterns can be generated with such a logic module and the test data output by the combinational logic systems, dependent on the random patterns, can be evaluated. However, the utilization of such uniformly distributed random patterns for testing digital modules having many combinational logic systems only enables an unsatisfactory fault coverage.